1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to an electrically erasable and programmable non-volatile semiconductor system including an array of memory cell transistors, and, more specifically, to a multi-level memory system wherein one memory cell has at least three memory states.
2. Description of the Related Art
With the increasing needs for high performance and high reliability of digital computer systems, it is demanding more and more to develop a large-capacity non-volatile semiconductor memory that can be an alternative to the existing external data-storage medium, such as a magnetic diskette, a fixed disk unit (which is also called the "hard disk unit"), or the like.
Recently, to fulfill the demand, a specific electrically erasable programmable non-volatile read-only memory (EEPROM) has been developed, wherein the integration density of memory cells is greatly enhanced by reducing the number of transistors required to form the cell array on a chip substrate of limited size. The EEPROM of this type is generally called a "NAND-cell type EEPROM" or "NAND type EEPROM," wherein a plurality of series circuits of floating gate tunneling metal oxide semiconductor (FATMOS) field effect transistors each serving as a 1-bit storage cell are arranged so that each of these circuits is connected to a corresponding bit line via a switching transistor. The switching transistor is rendered conductive, when designated, thereby to selectively connect a series circuit of memory cell transistors to a corresponding bit line associated therewith, and is called a "select transistor." The series cell-transistor circuits with the select transistors are called the "NAND cell units" in most cases.
Each NAND cell unit may include four, eight, or sixteen memory cell transistors, each of which has a control gate connected to a corresponding word line and a floating gate that may be charged with charge carriers selectively. Since each "memory cell" includes only one transistor, the integration density of the EEPROM can be improved to increase the total storage capacity thereof.
With presently available NAND type EEPROMs, the remaining non-selected memory cell transistors in each NAND cell unit serve as the "transfer gates" for transferring a data-bit to a target cell being presently selected during a write operation. Looking at a certain NAND cell unit, a select transistor turns on, causing this cell unit to be coupled to a corresponding bit line associated therewith. When a given cell transistor is selected, those non-selected memory cell transistors located between the select transistor and the selected cell transistor are rendered conductive (turn on). If a 1-bit data to be written (write-data) is of a specific logical level ("1" or "0," typically "1"), a data voltage supplied from the bit line is transferred to the selected cell transistor through the non-selected cell transistors. Charge carriers are injected from the drain to the floating gate of the selected cell transistor, charging the floating gate. The resultant threshold voltage of the selected cell transistor changes, causing the write-data to be programmed into the selected cell transistor.
To improve the operating reliability, the non-selected cell transistors serving as "data-transfer gates" during a write (program) or read operation are compelled to meet the following specific requirement: They are limited in variation of threshold voltages thereof. The threshold voltages of these cell transistors should not vary to fall out of a predetermined range (allowable variation range). Otherwise, the write-data to be programmed in the selected cell transistor itself will be varied in potential among the NAND cell units, with the result of the programming reliability being decreased.
With a presently available programming technique for NAND type EEPROMs, it is not easy to meet the above requirement. This may be based on the fact that a number of memory cell transistors on a chip substrate tend to differ from one another due to inherent deviation either in the manufacturing process or in the physical conditions or in the both thereof. Such threshold-voltage variation undesirably permits the coexistence of an easy-to-write cell and a difficult-to-write cell on the same chip substrate, which makes it difficult for an access operation to maintain consistency and uniformity throughout the cell transistors. The resultant operating reliability can no longer be excellent as required.
A similar problem lies behind the case of an erase operation. The resulting threshold voltage of a once-erased cell transistor--i.e., a cell transistor into which a logic "0" has been written-should be potentially greater than a predetermined negative level. Otherwise, a sufficient erase performance cannot be achieved; in the worst case, this may lead to the generation of an erase error. The threshold voltage of the erased cell transistor will affect the actual amount of a current (readout current) that may flow therein during a read period, which amount has strong concern with the data-accessing speed of EEPROMs. In this respect, the threshold-value control is very important. If an insufficiently erased memory cell remains after the erase operation, its resulting threshold voltage will increase beyond the upper-limit of the allowable variation range when a logic "1" is written thereinto during a subsequent program period. Such surplus of the threshold voltage causes the excess-write generation ratio to rise undesirably. As the integration density of the NAND type EEPROMs increases, the threshold-voltage control architecture for memory cells during write/erase operations will become more important and more serious.
The operation of the NAND type EEPROM and its problems will now be described more specifically.
A memory cell array having a FATMOS structure is integrated within a P-well formed in a p- or n-type substrate. The drain of a NAND cell is connected to a bit line through a select gate, while the source thereof is connected to a common source line through the select gate. The control gates of memory cells are arranged continuously in the row direction to serve as a word line.
To write data, a high voltage Vpp1 (=about 20 V) is applied to the control gate of a selected memory cell, an intermediate voltage Vppm (=about 10 V) is applied to the control and select gates of non-selected memory cells, and 0 V or intermediate voltage Vm (=about 8 V) is applied to the bit line. When 0 V is applied to the bit line, the voltage is transferred to the drain of the selected memory cell, and electrons are injected into a charge storage layer. The threshold voltage of the selected memory cell is thus shifted in the positive direction. For example, this state is defined as "1". In contrast, when Vm is applied to the bit line, no electrons are injected and thus the threshold voltage of the selected memory cell does not vary but remains negative. This is an erase state defined as "0". The data write operation is performed at once for memory cells having a common control gate.
The data erase operation is performed at once for all memory cells in the NAND cell. If 0 V is applied to all the control gates of the memory cells and Vpp2 (=about 20 V) is applied to the p-well, then the select gate, bit line and source line are all set to 20 V. Electrons are therefore discharged from the charge storage layers of all the memory cells to the P-well, and the threshold voltages of the memory cells are shifted in the negative direction.
The data read operation is carried out by applying 0 V to the control gate of the selected memory cell, applying a power supply voltage V.sub.CC (e.g., 5 V) to the control and select gates of the non-selected memory cells, and detecting whether a current flows through the selected memory cell.
After data "1" is written to a memory cell, the threshold voltage thereof has to be controlled to range between 0 V and V.sub.CC in view of the restriction of the read operation. For this reason, a write-verify is performed to detect only a "1" insufficient-written memory cell and set additional write data such that "1" data is additionally written to the insufficient-written memory cell (bit-by-bit verification).
The "1" insufficient-written memory cell can be detected by performing a verify read operation by setting the control gate of a selected memory cell to, e.g., 0.5 V (verify voltage). More specifically, if a memory cell has a margin for threshold voltage "0" and does not exceed 0.5 V, a current flows through a selected memory cell, it is detected as a "1" insufficient-written memory cell. Since a current naturally flows through a "0" written memory cell, a verify circuit for compensating the current flowing through the memory cell is provided in order to prevent the memory cell from being mistaken for a "1" insufficient-written memory cell. The verify circuit increases the speed of the write-verify.
If data is written by repeating the write and write-verify operations, the write time for each of the memory cells is optimized and the threshold voltage of the "1"-written memory cell is controlled to range between 0 V and V.sub.CC.
Let us consider that three write states "0", "1" and "2" are set when the power supply voltage V.sub.CC is, e.g., 5 V in order to achieve multi-level storing in the NAND type EEPROM. The threshold voltage in the "0" write state is not higher than 0 V, that in the "1" write state ranges, e.g., from 0 V to 2.5 V (=1/2 V.sub.CC), and that in the "2" write state ranges, e.g., from 2.5 V (=1/2 V.sub.CC) to 5 V (=V.sub.CC). In this EEPROM, therefore, the threshold voltages are set appropriately in the "0", "1" and "2" write states.
The threshold voltage of a memory cell varies as time elapses. For example, if a memory cell to which data is written is left alone, the charges of the charge storage layer are decreased by leakage current of an insulation film formed around the charge storage layer. The appropriate threshold voltage thus changes to a neutral threshold value. Consequently, the threshold voltage in the "0" write state is not higher than 0 V, that in the "1" write state ranges, e.g., from 0.5 V (0 V+0.5 V) to 2.0 V (=1/2 V.sub.CC -0.5 V), and that in the "2" write state ranges, e.g., from 3.0 V (=1/2 V.sub.CC +0.5 V) to 4.5 V (=V.sub.CC -0.5 V).
The threshold voltages cannot be sometimes set within a predetermined range even though the conventional bit-by-bit verify write operation is performed as described above. More specifically, since additional data is written to each insufficient-written memory cell in the bit-by-bit verify write operation, the lower limit of the threshold voltage of the memory cell is always secured, whereas the upper limit thereof is not verified and thus an excess write may occur. The following problem will therefore arise. Though an operator intends to write data "1", data "2" is actually written. In other words, whenever data "i" is written, data "i+1" and the following will be written.